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ASSEMBLY AND RELIABILITY ISSUES ASSOCIATED WITH LEADLESS CHIP SCALE PACKAGES
ASSEMBLY AND RELIABILITY ISSUES ASSOCIATED WITH LEADLESS CHIP SCALE PACKAGES
Muffadal Mukadam1, Michael Meilunas2, Peter Borgesen, Ph.D.3, K. Srihari, Ph.D.1
1Electronics Manufacturing Research and Services
State University of New York at Binghamton
Binghamton, NY 13902
2Process Research Engineer
Universal Instruments Corporation
Binghamton, NY 13902-0825
3Manager – Area Array Consortium
Universal Instruments Corporation
Binghamton, NY 13902-0825
ABSTRACT
This paper addresses the assembly and reliability of 0.5 mm pitch leadless Chip Scale Packages (CSP) on .062” immersion Ag plated printed circuit boards (PCB) using Pbfree solder paste. Four different leadless CSP designs were studied and each was evaluated using multiple PCB attachment pad designs.
Assembly was performed by stencil printing solder paste over the PCB pads, placing components with a high-speed placement machine, and reflowing in a forced convection oven. Vision issues were encountered during the placement process and a “video model” was required to place certain leadless packages.
Post assembly characterization included electrical measurements, visual inspection, X-ray inspection, and representative cross-sectioning to examine the 2nd level solder interconnects. Assemblies were subjected to 20- minute 0-100°C air-to-air thermal cycles. Cycle to failure (CTF) data was found to be quite sensitive to optimization of the solder paste printing process and, possibly, to the board pad dimensions.
INTRODUCTION
Leadless CSPs are leadframe packages characterized by their low assembly profile (see Figure 1), which may be 50% lower than traditional CSPs. Leadless packages are also lighter and fairly inexpensive. These packages are ideal for consumer electronic products, personal telecom, and datacom devices. Leadframe packages are also the preferred choice for RF applications due to their short lead length that results in low inductance and capacitance [8, 9].
Phenomenal growth is predicted for leadless package usage, with estimates of more than 1.8 billion in 2004 [8, 9], and the devices are expected to replace QFP, SOIC, and SOT style packages in the near future [8, 9].
Leadless CSPs require the creation of second level interconnections by deposition of either a solder paste or conductive adhesive. While they usually contain SnPb finishes, this is not a critical feature and replacement with either an Organic Solder Protect (OSP) coating or Ni/Au structure would readily facilitate a transition to Pb-free assembly. Notably, the industry is justifiably concerned about the unavoidable transition period during which some components will only be available with SnPb balls and others only with no-Pb. Any component offered without solder obviously leaves the choice of paste alloy up to the assembler. Three of the present packages discussed were supplied with a SnPb finish, while one package utilized a resin bump.
Leadless CSPs tend to be small and, because of their construction, are resistant to moisture and warpage. Most utilize a perimeter land array pattern with an exposed die paddle located beneath the silicon die (see Figure 1). The die paddle may be soldered directly to the PCB to enhance heat dissipation and electrical grounding (see Figure 2). The actual heat transfer efficiency can be further improved by the use of thermal vias from the PCB heat land to the ground planes.
A significant concern is, of course, assembly reliability.
Because of the much lower standoff, thermal mismatch induced strains in the solder joints are generally much larger than for bumped or leaded devices. While individual companies and industry consortia have been researching the issues [13] there is currently little published data on the reliability of leadless CSP assemblies.
Figure 1: Leadless Chip Scale Package [15]
Figure 2: Thermal Enhancement through Die Paddle [15]
The present work addresses Pb-free assembly and the resulting reliability of four representative leadless CSPs.
ASSEMBLY MATERIALS
Four different packages were considered in the present study, all square or nearly square with 40-48 I/O on 0.5 mm pitch. Three of the devices (A, B, C) were ¼” packages with terminations on all four sides, whereas the fourth device (D) was 0.43” long with terminations along two sides.
The four packages evaluated were similar in construction.
However, the packages varied in die dimensions and die paddle usage as summarized in Table 1.
Table 1: Package Description
The components were all soldered to immersion Ag plated copper pads on a 62 mil thick, high-Tg FR-4 printed circuit board using a type 3 no-clean 95.5Sn/3.8Ag/0.7Cu solder paste.
ASSEMBLY
Stencil Printing
Solder paste was deposited by printing through a 5 mil thick laser cut stencil using a 250 mm metal squeegee angled at 60°. The quality of the print deposits was assessed by visual inspection using an optical microscope after every print.
Four different aperture designs were considered for each package. Not surprisingly, the transfer efficiency varied with the ratio between the exposed PCB surface area and that of the aperture sidewalls in the usual fashion. Extensive clogging was observed in a number of cases, notably for three out of the four designs tried for package A which lead to insufficient paste deposition. As we shall see later, this had significant consequences, not only in terms of the risk of opens but also for the assembly reliability.
Two different designs were considered for the thermal pads on the PCB under packages A and B (see Figure 4): one with 25 thermal vias and one with four separated heat lands, respectively. Ideally, the die paddles should be soldered to these pads without significant voiding, but it may not be possible to eliminate voids completely because of the presence of the thermal vias and/or the large size of the thermal pad [14]. In addition, outgassing during reflow may cause solder balling especially if the solder paste coverage is large. Amkor recommends the use of multiple smaller stencil apertures instead of one big opening for printing on the thermal pads [14]. In the present work, however, we employed the simpler patterns showed in Figure 3. This did indeed lead to imperfect filling of the thermal vias as indicated by the X-ray images in Figure 5 and the cross section in Figure 6, but such details should have little or no effect on thermal cycling results.
Figure 3: Stencil Aperture For Exposed Die Paddle [4]
Figure 4: Heat Land Designs on PCB (Left – Heat Lands
with Thermal Vias, Right – Four Heat Land Design) [2, 4]
Leadless CSP
Thermal Enhancement Through Die Paddle Solder Paste Applied Using Stencil Printing
Figure 5: X-ray Image of Unfilled Thermal Vias on
Package B (left) and Package A (right) [5]
Figure 6: Cross-section of Unfilled Thermal Vias [5]
Component Placement
A four spindle flex head General Surface Mount (GSM) placement machine was used for component placement.
Components were supplied to the GSM in matrix trays and a placement force of 150 grams was used for placement.
Vision problems were encountered during component placement. This is because many leadless packages have poor contrast between the pad features and package background [11]. This reduces the ability of the vision system to distinguish between the features that have been assigned for the component recognition. Moreover, some of the leadless packages use a non-functional corner pad at 45° orientation [10]. These non-functional pads can be mistaken by the vision systems to be “pin 1” [10]. Leadless packages may also utilize unusually shaped corner pads whose geometry may not be recognizer by the placement machines (see Figure 7) [10, 11].
Figure 7: Leadless CSP with Odd Shaped Corner Pad
Reflow soldering
A previous study [6, 12] using a different no-Pb solder paste revealed higher assembly standoffs after reflow in air than after reflow in a nitrogen atmosphere, reflecting an incomplete collapse of the solder in the former. Also, reflow in air caused significant solder balling, an effect that was
eliminated by reflow in nitrogen (see Figure 8).
In the present study assemblies were reflown in a nitrogen atmosphere with less than 50 ppm oxygen in a 10 zone forced convection oven. The peak reflow temperature was relatively high at 250oC reflecting likely temperatures for the present components in a mass reflow with other, heavier ones. Time above liquidus was 54 seconds.
Figure 8: Solder Balling in Air Atmosphere [6, 12]
POST ASSEMBLY INSPECTION
Solder voiding
Voiding is not always critical in area array assembly, but in the present case it appeared to be. Leadless packages are generally susceptible to solder voiding, and significant voiding was indeed observed for all the packages. However, particularly extensive voiding was observed in package D assemblies. Figure 9 shows front and side cross-sectional views of typical joints, and Figure 10 shows an X-ray image of joints in a package D assembly.
In general, the solder voiding in a leadless package assembly is the result of a combination of factors [1, 2, 4, 5, 6, 12]:
§ The low standoff height which does not allow the voids to escape from open surfaces, instead entrapping them in the solder joint;
§ The coating on the lead finish which may contribute to the outgassing leading to void formation; and
§ The shape of the terminations.
Figure 9: Solder Voiding in Package D Assembly – Left:
Front Cross-sectional View, Right: Side Cross-sectional View [5]
Figure 10: X-ray Image of Package D [1]
Various numbers of solder joints were cross-sectioned for the different packages, and the solder joint and solder void areas were measured. Table 2 lists the average solder joint areas, the largest void areas and the average void areas for each.
Table 2: Solder Voiding in Different Packages [5]
Three of the packages have essentially the same joint area, while package C has considerably larger joints, as well as the largest standoff. The largest void area is seen to increase systematically with decreasing standoff across the four packages. As far as the average size of a void is concerned the effect is perhaps less obvious, but the largest standoff (package C) clearly leads to much smaller voids. Not surprising, there was also a clear effect of solder volume on the shapes and percentage of voids. Figure 11 shows a cross-sectional image of a joint resulting from insufficient solder deposition on a package A site.
Figure 11: Cross-sectional Image of Package A [5]
Standoff Measurements & Cross-sectional Analysis Figure 12 shows a cross-sectional view of package B. All cross-sectioned assemblies showed good wetting and the typical standoff height was assessed at 2.0 – 2.5 mil.
Moreover, good toe fillets were also found in these assemblies (refer Figure 13)
Figure 12: Cross-sectional Image of Package B [5]
Figure 13: Toe Fillets on Package B Assemblies
Figure 14 shows a cross-sectional view of package A.
Again, good wetting was observed. This was the only package with a metallized resin bump, rather than just a flat pad on the bottom. Together with a gap size essentially fixed by the solder between die paddle and PCB pad this lead to a minimum solder height of less than 1 mil. While
this is not inherently a problem for reliability, (the resin presumably offers compliance and reduces thermal cycling stresses on the solder), it had a clear effect on voiding (see Table 2).
Figure 14: Cross-sectional Image of Package A [5]
Figure 15 shows a cross-sectional view of package C. Good wetting was again observed and the standoff was slightly larger (2.5 mil) than with package B.
Finally, Figure 9 shows a cross-sectional view of package D, for which smaller stencil apertures relative to the corresponding pad areas led to a smaller standoff height of about 1.5 mil.
Figure 15: Cross-sectional Image of Package C [5]
In general, there were no significant differences between the standoffs for the same packages assembled to different PCB pad sizes [6. 12] because the stencil design always incorporated larger apertures for larger PCB pads.
RELIABILITY RESULTS
Each combination of package, substrate pad and solder mask design, and stencil aperture design was subjected to 0- 100oC air-to-air thermal cycling with 5 minute ramps and 5 minute holds. Afterwards dye penetration tests were performed on 6 samples of each of the failed component types. Figure 16 indicates the frequency of completely cracked joints versus location within the solder joint arrays for packages D, B, and C. Packages B and D are seen to behave as expected, with the joints furthest from the package center (neutral point) being most susceptible to failure during thermal cycling. In the case of package C, however, failures appeared to be randomly located within the package footprint (see Figure 16) [7, 13]. Figure 17 shows three adjacent solder joints of package C subjected to dye penetration test. Solder fatigue is represented by red dye.
Although the joints are located next to each other, the degree of fatigue is seen to vary considerably. The reasons for this are still under investigation.
Figure 16: Dye Penetration Results for packages D, B
and C [7, 13]
Figure 17: Dye Penetration Test on Package C [7, 13]
Once a significant number of failures were recorded, a Weibull distribution was produced and the slopes and characteristic lifetimes, N63, of the assemblies were determined.
None of the package B assemblies failed through 5000 thermal cycles, presumably because of the lack of a Si die in the package. Soldering of the die paddle to the PCB is also expected to provide some stress relief for the solder joints along the edge, but the other package with a die paddle, package A, experienced many failures. In fact, package A failed earlier than the similarly sized package C which did not have an exposed die paddle.
The overall package performance indicates that the reliability of package C is superior to that of packages D and A. Package D demonstrated the lowest characteristic life.
This is not surprising given that package D was the largest device, contained solder joints with the lowest standoff and with numerous voids.
The effects of pad and stencil size were evaluated for the three devices with failures. As expected, larger stencil apertures (greater transfer efficiencies) were shown to improve reliability. The results also indicate that an optimization of pad area and pad dimensions exists. In other words a long, thin pad may not produce the same reliability as a shorter, wider pad with an identical surface area.
However, the pad variations studied were limited and prevent us from further comment. Overall, there seems to be little doubt that the reliability of the present leadless packages may be strongly affected by stencil design.
Packages A and C showed a systematic effect of stencil aperture and pad design. Larger apertures (greater transfer efficiency) combined with larger PCB pads clearly improved reliability. Sensitivity to aperture clogging and paste deposit insufficiency for package A has been previously discussed, and optimizing the aperture design (increasing the area ratio) and increasing the pad size resulted in an N63 increase from 1280 to 1962 cycles. The reliability improvement was attributed to slightly larger solder volumes, and more importantly, to the significant reduction in joint volume scatter invariably achieved by such optimization. In other words, there was a preferential elimination of the smallest joints with the most/largest voids. Further evidence of such is apparent when comparing the failure distributions provided by the Weibull slope. The Weibull slope indicates that the pad and stencil optimization was accompanied by a tightening of the failure distribution by a factor of about two, i.e. a preferential elimination (or delay) of the earliest failures (which are most often of practical concern).
A similar optimization had less effect for package C, which had a much larger standoff and thus fewer, smaller voids (Table 2). However, among the variables considered, an increase in N63 from 2063 to 2498 cycles appeared to be related to an increase in minimum pad width (and thus solder joint width and the crack length needed for failure) and/or stencil aperture transfer efficiency. Once again we emphasize that a moderate increase in the area ratio is generally known to affect the scatter in solder paste volume more than the average. As the increase in N63 was again accompanied by a systematic tightening of the failure distribution (70% increase in Weibull slope), it again seems most likely that the improvement is related to the preferential elimination of relatively small solder joint volumes with relatively large voids. This might also account for the apparent randomness of failure location observed for this component.
The results for Package D indicate a systematic dependence on pad size. The Package D N63 increased linearly (from 803 to 1193 cycles) with increasing pad area and thus solder joint cross section. However, in this case there is no indication of a dependence on minimum pad width (and package C showed no correlation between N63 and pad area). On the other hand, the largest N63 again corresponded also to the tightest failure distribution and stencil apertures optimized to minimize the scatter in solder deposit volume.
CONCLUSIONS
Commercially available leadless CSPs were readily assembled onto high-Tg boards with Pb-free solder paste.
Assembly reliability appeared quite sensitive to the proper optimization of the PCB pad and stencil aperture design, presumably through a minimization of the scatter in solder joint volume and voiding. It follows that further reduction in voiding through materials selection and process optimization may offer additional benefits.
In general, lifetimes in excess of 1000 cycles between 0oC and 100oC seem achievable with these packages on 62 mil thick boards. However, we caution that two assemblies involved low-level Pb contamination of the no-Pb solder joints. The effects of this are expected to depend on the relative volumes, reflow profile parameters and subsequent thermal history, as well as assembly mechanics and detailed accelerated test parameters. We are currently researching the mechanisms behind such dependencies, but at this point we would consider it very risky to extrapolate our results to very different test conditions or ‘life in service’.
References
1. Gowda, A. and Srihari, K., “Characterization of
CSPTB-5 Assembly at Rockwell Automation”,
Technical Report, Area Array Consortium, Universal
Instruments Corporation, Binghamton, NY, 2002.
2. Esler, D. and Srihari, K., “Characterization of CSPTB-7
Build at MSL”, Technical Report Area Array
Consortium, Universal Instruments Corporation,
Binghamton, NY, 2002.
3. Lau, J., Lee, R.S., and Lee, S.W., “Chip Scale Package:
Design, Materials, Process, Reliability, and
Applications”, McGraw Hill Professional Publishing,
NY, 1999.
4. Vinod, M., Hartono, H., Marquez, U., Esler, D., and
Srihari, K., “Lead-free Component Assembly of
CSPTB-6 (Rockwell Automation)”, Technical Report,
Area Array Consortium, Universal Instruments
Corporation, Binghamton, NY, 2002.
5. Mukadam, M. and Srihari, K., “Assembly of Flip Chip
CSPs and Leadless CSPs on Test Board 6”, Technical
Report, Area Array Consortium, Universal Instruments
Corporation, Binghamton, NY 2002.
6. Joshi, J., Yunus, M., & Srihari, K., “Assembly Of
CSPs, WLCSPs And Micro Lead Frame Packages On
Test Board-5” Area Array Consortium, Universal
Instruments Corporation, Binghamton, New York,
2000.
7. Meilunas, M., “Reliability Assessment of Leadless Chip
Scale Packages in Air to Air Thermal Cycling”, Area
Array Consortium, Universal Instruments Corporation,
Binghamton, New York, December 2000.
8. Comley, D., Smith, P., “The QFN: Smaller, Faster and
Less Expensive”, Chip Scale Review, Aug – Sept 2002.
9. Berry, S., Winkler, S., “Radio Frequency ICs Gaining:
Leadframe Packages Favored”, Chip Scale Review,
March 2003.
10. Westby, G., “MLF Assembly Challenges”, Circuits
Assembly, October 2002.
11. Dunlap, M., “TB7 Consortium Builds At
Manufacturer’s Services Ltd.”, Area Array Consortium,
Universal Instruments Corporation, Binghamton, New
York, December 2002.
12. Joshi, J., Yunus, M., & Srihari, K., “Lead-free
Assembly of Leadless CSPs” Area Array Consortium,
Universal Instruments Corporation, Binghamton, New
York, 2000.
13. Meilunas, M., “Lead-free and Sn/Pb Leadless Chip
Scale Package Reliability”, Area Array Consortium,
Universal Instruments Corporation, Binghamton, New
York, December 2000.
14. Amkor, “Application Notes for Surface Mount
Assembly of Amkor’s MicroLeadFrame (MLF)
Packages”, www.amkor.com, September 2002.
15. Mukadam, M., “WTSN 581 Assignment 2”, WTSN 581
Class Assignment, Binghamton University, Spring
2002. ¶ 8:10 오후 0개의 덧글
Muffadal Mukadam1, Michael Meilunas2, Peter Borgesen, Ph.D.3, K. Srihari, Ph.D.1
1Electronics Manufacturing Research and Services
State University of New York at Binghamton
Binghamton, NY 13902
2Process Research Engineer
Universal Instruments Corporation
Binghamton, NY 13902-0825
3Manager – Area Array Consortium
Universal Instruments Corporation
Binghamton, NY 13902-0825
ABSTRACT
This paper addresses the assembly and reliability of 0.5 mm pitch leadless Chip Scale Packages (CSP) on .062” immersion Ag plated printed circuit boards (PCB) using Pbfree solder paste. Four different leadless CSP designs were studied and each was evaluated using multiple PCB attachment pad designs.
Assembly was performed by stencil printing solder paste over the PCB pads, placing components with a high-speed placement machine, and reflowing in a forced convection oven. Vision issues were encountered during the placement process and a “video model” was required to place certain leadless packages.
Post assembly characterization included electrical measurements, visual inspection, X-ray inspection, and representative cross-sectioning to examine the 2nd level solder interconnects. Assemblies were subjected to 20- minute 0-100°C air-to-air thermal cycles. Cycle to failure (CTF) data was found to be quite sensitive to optimization of the solder paste printing process and, possibly, to the board pad dimensions.
INTRODUCTION
Leadless CSPs are leadframe packages characterized by their low assembly profile (see Figure 1), which may be 50% lower than traditional CSPs. Leadless packages are also lighter and fairly inexpensive. These packages are ideal for consumer electronic products, personal telecom, and datacom devices. Leadframe packages are also the preferred choice for RF applications due to their short lead length that results in low inductance and capacitance [8, 9].
Phenomenal growth is predicted for leadless package usage, with estimates of more than 1.8 billion in 2004 [8, 9], and the devices are expected to replace QFP, SOIC, and SOT style packages in the near future [8, 9].
Leadless CSPs require the creation of second level interconnections by deposition of either a solder paste or conductive adhesive. While they usually contain SnPb finishes, this is not a critical feature and replacement with either an Organic Solder Protect (OSP) coating or Ni/Au structure would readily facilitate a transition to Pb-free assembly. Notably, the industry is justifiably concerned about the unavoidable transition period during which some components will only be available with SnPb balls and others only with no-Pb. Any component offered without solder obviously leaves the choice of paste alloy up to the assembler. Three of the present packages discussed were supplied with a SnPb finish, while one package utilized a resin bump.
Leadless CSPs tend to be small and, because of their construction, are resistant to moisture and warpage. Most utilize a perimeter land array pattern with an exposed die paddle located beneath the silicon die (see Figure 1). The die paddle may be soldered directly to the PCB to enhance heat dissipation and electrical grounding (see Figure 2). The actual heat transfer efficiency can be further improved by the use of thermal vias from the PCB heat land to the ground planes.
A significant concern is, of course, assembly reliability.
Because of the much lower standoff, thermal mismatch induced strains in the solder joints are generally much larger than for bumped or leaded devices. While individual companies and industry consortia have been researching the issues [13] there is currently little published data on the reliability of leadless CSP assemblies.
Figure 1: Leadless Chip Scale Package [15]
Figure 2: Thermal Enhancement through Die Paddle [15]
The present work addresses Pb-free assembly and the resulting reliability of four representative leadless CSPs.
ASSEMBLY MATERIALS
Four different packages were considered in the present study, all square or nearly square with 40-48 I/O on 0.5 mm pitch. Three of the devices (A, B, C) were ¼” packages with terminations on all four sides, whereas the fourth device (D) was 0.43” long with terminations along two sides.
The four packages evaluated were similar in construction.
However, the packages varied in die dimensions and die paddle usage as summarized in Table 1.
Table 1: Package Description
The components were all soldered to immersion Ag plated copper pads on a 62 mil thick, high-Tg FR-4 printed circuit board using a type 3 no-clean 95.5Sn/3.8Ag/0.7Cu solder paste.
ASSEMBLY
Stencil Printing
Solder paste was deposited by printing through a 5 mil thick laser cut stencil using a 250 mm metal squeegee angled at 60°. The quality of the print deposits was assessed by visual inspection using an optical microscope after every print.
Four different aperture designs were considered for each package. Not surprisingly, the transfer efficiency varied with the ratio between the exposed PCB surface area and that of the aperture sidewalls in the usual fashion. Extensive clogging was observed in a number of cases, notably for three out of the four designs tried for package A which lead to insufficient paste deposition. As we shall see later, this had significant consequences, not only in terms of the risk of opens but also for the assembly reliability.
Two different designs were considered for the thermal pads on the PCB under packages A and B (see Figure 4): one with 25 thermal vias and one with four separated heat lands, respectively. Ideally, the die paddles should be soldered to these pads without significant voiding, but it may not be possible to eliminate voids completely because of the presence of the thermal vias and/or the large size of the thermal pad [14]. In addition, outgassing during reflow may cause solder balling especially if the solder paste coverage is large. Amkor recommends the use of multiple smaller stencil apertures instead of one big opening for printing on the thermal pads [14]. In the present work, however, we employed the simpler patterns showed in Figure 3. This did indeed lead to imperfect filling of the thermal vias as indicated by the X-ray images in Figure 5 and the cross section in Figure 6, but such details should have little or no effect on thermal cycling results.
Figure 3: Stencil Aperture For Exposed Die Paddle [4]
Figure 4: Heat Land Designs on PCB (Left – Heat Lands
with Thermal Vias, Right – Four Heat Land Design) [2, 4]
Leadless CSP
Thermal Enhancement Through Die Paddle Solder Paste Applied Using Stencil Printing
Figure 5: X-ray Image of Unfilled Thermal Vias on
Package B (left) and Package A (right) [5]
Figure 6: Cross-section of Unfilled Thermal Vias [5]
Component Placement
A four spindle flex head General Surface Mount (GSM) placement machine was used for component placement.
Components were supplied to the GSM in matrix trays and a placement force of 150 grams was used for placement.
Vision problems were encountered during component placement. This is because many leadless packages have poor contrast between the pad features and package background [11]. This reduces the ability of the vision system to distinguish between the features that have been assigned for the component recognition. Moreover, some of the leadless packages use a non-functional corner pad at 45° orientation [10]. These non-functional pads can be mistaken by the vision systems to be “pin 1” [10]. Leadless packages may also utilize unusually shaped corner pads whose geometry may not be recognizer by the placement machines (see Figure 7) [10, 11].
Figure 7: Leadless CSP with Odd Shaped Corner Pad
Reflow soldering
A previous study [6, 12] using a different no-Pb solder paste revealed higher assembly standoffs after reflow in air than after reflow in a nitrogen atmosphere, reflecting an incomplete collapse of the solder in the former. Also, reflow in air caused significant solder balling, an effect that was
eliminated by reflow in nitrogen (see Figure 8).
In the present study assemblies were reflown in a nitrogen atmosphere with less than 50 ppm oxygen in a 10 zone forced convection oven. The peak reflow temperature was relatively high at 250oC reflecting likely temperatures for the present components in a mass reflow with other, heavier ones. Time above liquidus was 54 seconds.
Figure 8: Solder Balling in Air Atmosphere [6, 12]
POST ASSEMBLY INSPECTION
Solder voiding
Voiding is not always critical in area array assembly, but in the present case it appeared to be. Leadless packages are generally susceptible to solder voiding, and significant voiding was indeed observed for all the packages. However, particularly extensive voiding was observed in package D assemblies. Figure 9 shows front and side cross-sectional views of typical joints, and Figure 10 shows an X-ray image of joints in a package D assembly.
In general, the solder voiding in a leadless package assembly is the result of a combination of factors [1, 2, 4, 5, 6, 12]:
§ The low standoff height which does not allow the voids to escape from open surfaces, instead entrapping them in the solder joint;
§ The coating on the lead finish which may contribute to the outgassing leading to void formation; and
§ The shape of the terminations.
Figure 9: Solder Voiding in Package D Assembly – Left:
Front Cross-sectional View, Right: Side Cross-sectional View [5]
Figure 10: X-ray Image of Package D [1]
Various numbers of solder joints were cross-sectioned for the different packages, and the solder joint and solder void areas were measured. Table 2 lists the average solder joint areas, the largest void areas and the average void areas for each.
Table 2: Solder Voiding in Different Packages [5]
Three of the packages have essentially the same joint area, while package C has considerably larger joints, as well as the largest standoff. The largest void area is seen to increase systematically with decreasing standoff across the four packages. As far as the average size of a void is concerned the effect is perhaps less obvious, but the largest standoff (package C) clearly leads to much smaller voids. Not surprising, there was also a clear effect of solder volume on the shapes and percentage of voids. Figure 11 shows a cross-sectional image of a joint resulting from insufficient solder deposition on a package A site.
Figure 11: Cross-sectional Image of Package A [5]
Standoff Measurements & Cross-sectional Analysis Figure 12 shows a cross-sectional view of package B. All cross-sectioned assemblies showed good wetting and the typical standoff height was assessed at 2.0 – 2.5 mil.
Moreover, good toe fillets were also found in these assemblies (refer Figure 13)
Figure 12: Cross-sectional Image of Package B [5]
Figure 13: Toe Fillets on Package B Assemblies
Figure 14 shows a cross-sectional view of package A.
Again, good wetting was observed. This was the only package with a metallized resin bump, rather than just a flat pad on the bottom. Together with a gap size essentially fixed by the solder between die paddle and PCB pad this lead to a minimum solder height of less than 1 mil. While
this is not inherently a problem for reliability, (the resin presumably offers compliance and reduces thermal cycling stresses on the solder), it had a clear effect on voiding (see Table 2).
Figure 14: Cross-sectional Image of Package A [5]
Figure 15 shows a cross-sectional view of package C. Good wetting was again observed and the standoff was slightly larger (2.5 mil) than with package B.
Finally, Figure 9 shows a cross-sectional view of package D, for which smaller stencil apertures relative to the corresponding pad areas led to a smaller standoff height of about 1.5 mil.
Figure 15: Cross-sectional Image of Package C [5]
In general, there were no significant differences between the standoffs for the same packages assembled to different PCB pad sizes [6. 12] because the stencil design always incorporated larger apertures for larger PCB pads.
RELIABILITY RESULTS
Each combination of package, substrate pad and solder mask design, and stencil aperture design was subjected to 0- 100oC air-to-air thermal cycling with 5 minute ramps and 5 minute holds. Afterwards dye penetration tests were performed on 6 samples of each of the failed component types. Figure 16 indicates the frequency of completely cracked joints versus location within the solder joint arrays for packages D, B, and C. Packages B and D are seen to behave as expected, with the joints furthest from the package center (neutral point) being most susceptible to failure during thermal cycling. In the case of package C, however, failures appeared to be randomly located within the package footprint (see Figure 16) [7, 13]. Figure 17 shows three adjacent solder joints of package C subjected to dye penetration test. Solder fatigue is represented by red dye.
Although the joints are located next to each other, the degree of fatigue is seen to vary considerably. The reasons for this are still under investigation.
Figure 16: Dye Penetration Results for packages D, B
and C [7, 13]
Figure 17: Dye Penetration Test on Package C [7, 13]
Once a significant number of failures were recorded, a Weibull distribution was produced and the slopes and characteristic lifetimes, N63, of the assemblies were determined.
None of the package B assemblies failed through 5000 thermal cycles, presumably because of the lack of a Si die in the package. Soldering of the die paddle to the PCB is also expected to provide some stress relief for the solder joints along the edge, but the other package with a die paddle, package A, experienced many failures. In fact, package A failed earlier than the similarly sized package C which did not have an exposed die paddle.
The overall package performance indicates that the reliability of package C is superior to that of packages D and A. Package D demonstrated the lowest characteristic life.
This is not surprising given that package D was the largest device, contained solder joints with the lowest standoff and with numerous voids.
The effects of pad and stencil size were evaluated for the three devices with failures. As expected, larger stencil apertures (greater transfer efficiencies) were shown to improve reliability. The results also indicate that an optimization of pad area and pad dimensions exists. In other words a long, thin pad may not produce the same reliability as a shorter, wider pad with an identical surface area.
However, the pad variations studied were limited and prevent us from further comment. Overall, there seems to be little doubt that the reliability of the present leadless packages may be strongly affected by stencil design.
Packages A and C showed a systematic effect of stencil aperture and pad design. Larger apertures (greater transfer efficiency) combined with larger PCB pads clearly improved reliability. Sensitivity to aperture clogging and paste deposit insufficiency for package A has been previously discussed, and optimizing the aperture design (increasing the area ratio) and increasing the pad size resulted in an N63 increase from 1280 to 1962 cycles. The reliability improvement was attributed to slightly larger solder volumes, and more importantly, to the significant reduction in joint volume scatter invariably achieved by such optimization. In other words, there was a preferential elimination of the smallest joints with the most/largest voids. Further evidence of such is apparent when comparing the failure distributions provided by the Weibull slope. The Weibull slope indicates that the pad and stencil optimization was accompanied by a tightening of the failure distribution by a factor of about two, i.e. a preferential elimination (or delay) of the earliest failures (which are most often of practical concern).
A similar optimization had less effect for package C, which had a much larger standoff and thus fewer, smaller voids (Table 2). However, among the variables considered, an increase in N63 from 2063 to 2498 cycles appeared to be related to an increase in minimum pad width (and thus solder joint width and the crack length needed for failure) and/or stencil aperture transfer efficiency. Once again we emphasize that a moderate increase in the area ratio is generally known to affect the scatter in solder paste volume more than the average. As the increase in N63 was again accompanied by a systematic tightening of the failure distribution (70% increase in Weibull slope), it again seems most likely that the improvement is related to the preferential elimination of relatively small solder joint volumes with relatively large voids. This might also account for the apparent randomness of failure location observed for this component.
The results for Package D indicate a systematic dependence on pad size. The Package D N63 increased linearly (from 803 to 1193 cycles) with increasing pad area and thus solder joint cross section. However, in this case there is no indication of a dependence on minimum pad width (and package C showed no correlation between N63 and pad area). On the other hand, the largest N63 again corresponded also to the tightest failure distribution and stencil apertures optimized to minimize the scatter in solder deposit volume.
CONCLUSIONS
Commercially available leadless CSPs were readily assembled onto high-Tg boards with Pb-free solder paste.
Assembly reliability appeared quite sensitive to the proper optimization of the PCB pad and stencil aperture design, presumably through a minimization of the scatter in solder joint volume and voiding. It follows that further reduction in voiding through materials selection and process optimization may offer additional benefits.
In general, lifetimes in excess of 1000 cycles between 0oC and 100oC seem achievable with these packages on 62 mil thick boards. However, we caution that two assemblies involved low-level Pb contamination of the no-Pb solder joints. The effects of this are expected to depend on the relative volumes, reflow profile parameters and subsequent thermal history, as well as assembly mechanics and detailed accelerated test parameters. We are currently researching the mechanisms behind such dependencies, but at this point we would consider it very risky to extrapolate our results to very different test conditions or ‘life in service’.
References
1. Gowda, A. and Srihari, K., “Characterization of
CSPTB-5 Assembly at Rockwell Automation”,
Technical Report, Area Array Consortium, Universal
Instruments Corporation, Binghamton, NY, 2002.
2. Esler, D. and Srihari, K., “Characterization of CSPTB-7
Build at MSL”, Technical Report Area Array
Consortium, Universal Instruments Corporation,
Binghamton, NY, 2002.
3. Lau, J., Lee, R.S., and Lee, S.W., “Chip Scale Package:
Design, Materials, Process, Reliability, and
Applications”, McGraw Hill Professional Publishing,
NY, 1999.
4. Vinod, M., Hartono, H., Marquez, U., Esler, D., and
Srihari, K., “Lead-free Component Assembly of
CSPTB-6 (Rockwell Automation)”, Technical Report,
Area Array Consortium, Universal Instruments
Corporation, Binghamton, NY, 2002.
5. Mukadam, M. and Srihari, K., “Assembly of Flip Chip
CSPs and Leadless CSPs on Test Board 6”, Technical
Report, Area Array Consortium, Universal Instruments
Corporation, Binghamton, NY 2002.
6. Joshi, J., Yunus, M., & Srihari, K., “Assembly Of
CSPs, WLCSPs And Micro Lead Frame Packages On
Test Board-5” Area Array Consortium, Universal
Instruments Corporation, Binghamton, New York,
2000.
7. Meilunas, M., “Reliability Assessment of Leadless Chip
Scale Packages in Air to Air Thermal Cycling”, Area
Array Consortium, Universal Instruments Corporation,
Binghamton, New York, December 2000.
8. Comley, D., Smith, P., “The QFN: Smaller, Faster and
Less Expensive”, Chip Scale Review, Aug – Sept 2002.
9. Berry, S., Winkler, S., “Radio Frequency ICs Gaining:
Leadframe Packages Favored”, Chip Scale Review,
March 2003.
10. Westby, G., “MLF Assembly Challenges”, Circuits
Assembly, October 2002.
11. Dunlap, M., “TB7 Consortium Builds At
Manufacturer’s Services Ltd.”, Area Array Consortium,
Universal Instruments Corporation, Binghamton, New
York, December 2002.
12. Joshi, J., Yunus, M., & Srihari, K., “Lead-free
Assembly of Leadless CSPs” Area Array Consortium,
Universal Instruments Corporation, Binghamton, New
York, 2000.
13. Meilunas, M., “Lead-free and Sn/Pb Leadless Chip
Scale Package Reliability”, Area Array Consortium,
Universal Instruments Corporation, Binghamton, New
York, December 2000.
14. Amkor, “Application Notes for Surface Mount
Assembly of Amkor’s MicroLeadFrame (MLF)
Packages”, www.amkor.com, September 2002.
15. Mukadam, M., “WTSN 581 Assignment 2”, WTSN 581
Class Assignment, Binghamton University, Spring
2002. ¶ 8:10 오후 0개의 덧글
목요일, 3월 08, 2007
혹시나 사무라이 참프루 인트로 화면에서 나오는 글씨체를 궁금해 하는분들이 있을꺼 같아서 올려봅니다.
글씨체 이름은 " brooklyn kid " 라는 글씨체랍니다!
¶ 6:09 오후 0개의 덧글
수요일, 3월 07, 2007
화요일, 3월 06, 2007
알기쉬운 주택임대차 보호법
[강근호의 부동산 세상]
김동산씨는 전 재산 4000만원으로 전세를 얻으려고 하는데 무엇을 어떻게 해야 할지 난감하다. 법적으로 전 재산 4000만원을 날리지 않을까 하는 걱정 때문이다.
전세 또는 월세로 들어가려면 무엇부터 해야 하는가? 오늘은 주택임대차보호법(이하 동법)에 대해 알아보겠다.
첫째, 해당 물건의 등기부부터 확인해야 한다. 등기부에 근저당권 등이 기재되어 있다면 그 채권액을 살펴보아야 한다.
만일 건물의 매매가에 비하여 근저당금액이 50~70%를 초과한다면 위험한 집이라고 할 수 있다.
또 소유주의 직업을 확인하는 것도 잊지 말아야 한다. 사업으로 자주 돈이 필요한 경우라면 당연히 위험성이 높을 수밖에 없기 때문이다.
둘째, 계약을 하게 되면 일단 동사무소에 가서 주민등록을 하고 계약서에 확정일자를 받아야 한다. 주민등록을 하면 집주인이 집을 팔더라도 약정기간 그 집에 계속 거주할 수 있다.
만일 주민등록을 하지 않으면 새 주인이 나가라고 할 경우 자신의 권리를 주장할 수 없게 된다.
그리고 확정일자를 받아두어야 훗날 임차주택이 경매로 넘어갈 때 자신의 보증금을 법원에 신고한 후배당에 참가하여 보증금을 변제받을 수 있다.
이를 보증금의 우선변제권이라 하는데 선순위 채권자가 많은 경우 한 푼도 받지 못할 위험이 생길 수 있다.
따라서 동법에서는 이러한 우선변제권 이외에도 최우선변제권을 규정하고 있다. 서울지역 등에서는 보증금액이 4000만원 이하인 경우만 1600만원을 최우선적으로 배당해준다.
셋째, 계약서를 작성할 경우 아주 오래 머물지 않을 것이라면 가급적 기간을 1년으로 하는 것이 좋다.
왜냐하면 1년을 계약하더라도 임차인으로서는 2년을 주장할 수도 있기 때문이다.
만일 2년을 약정하였는데 1년 만에 집을 비워야 할 사정이 발생한다면 스스로 다른 임차인을 구해야 하는 번거로움이 생긴다.
따라서 1년을 약정한 후 더 살고 싶으면 1년을 더 살 수 있다. 이는 동법이 거주기간을 2년으로 보장하고 있기 때문이다.
넷째, 임대차 기간이 만료될 즈음 보증금을 반환받고 바로 기간만료 일자에 임대차를 종료해 이사하고 싶을 경우 법정갱신제도에 주의해야 한다.
임차인이 기간만료시점에 보증금을 반환받기 위해서는 기간만료 1개월 전까지 그런 사정을 내용증명으로 통보해야 한다. 그렇지 않으면 자동적으로 재계약이 되어 해지통보시점부터 다시 3개월을 기다려야만 하기 때문이다.
다섯째, 임대차기간이 만료되었는데도 불구하고 임대인(집주인)측에서 방이 안 빠진다고 자꾸 기다리라고만 할 경우에 임차인은 임차주택을 관할하는 지방법원이나 지방법원지원, 또는 시군법원에 가서 단독으로 임차권등기명령을 신청할 수 있다.
또한 임차권등기명령 신청에 따른 비용은 임대인에게 전액 청구할 수 있다. 임차인은 임차권등기명령에 의한 임차권등기가 된 후에 집을 비우고 이사해도 된다.
임대인이 계속해서 보증금을 반환해주지 않을 경우 임차인은 보증금반환청구소송(소액사건절차법에 의하여 비교적 간단히 소송을 제기할 수 있다)에서 확정판결을 받아 법원에 강제경매를 신청하여 보증금을 배당받을 수 있게 된다.
다만, 실무상으로는 임차권등기 후 법원에 지급명령을 신청하는 경우도 많이 볼 수 있다.
강근호 노량진 이그잼고시학원 공인중개사 민법 선생님
데일리노컷뉴스 ¶ 12:38 오후 0개의 덧글
김동산씨는 전 재산 4000만원으로 전세를 얻으려고 하는데 무엇을 어떻게 해야 할지 난감하다. 법적으로 전 재산 4000만원을 날리지 않을까 하는 걱정 때문이다.
전세 또는 월세로 들어가려면 무엇부터 해야 하는가? 오늘은 주택임대차보호법(이하 동법)에 대해 알아보겠다.
첫째, 해당 물건의 등기부부터 확인해야 한다. 등기부에 근저당권 등이 기재되어 있다면 그 채권액을 살펴보아야 한다.
만일 건물의 매매가에 비하여 근저당금액이 50~70%를 초과한다면 위험한 집이라고 할 수 있다.
또 소유주의 직업을 확인하는 것도 잊지 말아야 한다. 사업으로 자주 돈이 필요한 경우라면 당연히 위험성이 높을 수밖에 없기 때문이다.
둘째, 계약을 하게 되면 일단 동사무소에 가서 주민등록을 하고 계약서에 확정일자를 받아야 한다. 주민등록을 하면 집주인이 집을 팔더라도 약정기간 그 집에 계속 거주할 수 있다.
만일 주민등록을 하지 않으면 새 주인이 나가라고 할 경우 자신의 권리를 주장할 수 없게 된다.
그리고 확정일자를 받아두어야 훗날 임차주택이 경매로 넘어갈 때 자신의 보증금을 법원에 신고한 후배당에 참가하여 보증금을 변제받을 수 있다.
이를 보증금의 우선변제권이라 하는데 선순위 채권자가 많은 경우 한 푼도 받지 못할 위험이 생길 수 있다.
따라서 동법에서는 이러한 우선변제권 이외에도 최우선변제권을 규정하고 있다. 서울지역 등에서는 보증금액이 4000만원 이하인 경우만 1600만원을 최우선적으로 배당해준다.
셋째, 계약서를 작성할 경우 아주 오래 머물지 않을 것이라면 가급적 기간을 1년으로 하는 것이 좋다.
왜냐하면 1년을 계약하더라도 임차인으로서는 2년을 주장할 수도 있기 때문이다.
만일 2년을 약정하였는데 1년 만에 집을 비워야 할 사정이 발생한다면 스스로 다른 임차인을 구해야 하는 번거로움이 생긴다.
따라서 1년을 약정한 후 더 살고 싶으면 1년을 더 살 수 있다. 이는 동법이 거주기간을 2년으로 보장하고 있기 때문이다.
넷째, 임대차 기간이 만료될 즈음 보증금을 반환받고 바로 기간만료 일자에 임대차를 종료해 이사하고 싶을 경우 법정갱신제도에 주의해야 한다.
임차인이 기간만료시점에 보증금을 반환받기 위해서는 기간만료 1개월 전까지 그런 사정을 내용증명으로 통보해야 한다. 그렇지 않으면 자동적으로 재계약이 되어 해지통보시점부터 다시 3개월을 기다려야만 하기 때문이다.
다섯째, 임대차기간이 만료되었는데도 불구하고 임대인(집주인)측에서 방이 안 빠진다고 자꾸 기다리라고만 할 경우에 임차인은 임차주택을 관할하는 지방법원이나 지방법원지원, 또는 시군법원에 가서 단독으로 임차권등기명령을 신청할 수 있다.
또한 임차권등기명령 신청에 따른 비용은 임대인에게 전액 청구할 수 있다. 임차인은 임차권등기명령에 의한 임차권등기가 된 후에 집을 비우고 이사해도 된다.
임대인이 계속해서 보증금을 반환해주지 않을 경우 임차인은 보증금반환청구소송(소액사건절차법에 의하여 비교적 간단히 소송을 제기할 수 있다)에서 확정판결을 받아 법원에 강제경매를 신청하여 보증금을 배당받을 수 있게 된다.
다만, 실무상으로는 임차권등기 후 법원에 지급명령을 신청하는 경우도 많이 볼 수 있다.
강근호 노량진 이그잼고시학원 공인중개사 민법 선생님
데일리노컷뉴스 ¶ 12:38 오후 0개의 덧글
토요일, 3월 03, 2007
금요일, 3월 02, 2007
2004년7월 [삼성전자]신개념 반도체 조립기술 개발
[삼성전자]
신개념 반도체 조립기술 개발
[2004년 7월 뉴스파노라마]
지금까지 사용되던 반도체 패키지(조립) 방식과는 차원이 다른 신개념의 반도체 패키지 기술을 선보였다. 삼성전자는 반도체 칩을 분리하지 않은 Wafer 상태에서 칩에 패키지를 씌우는'웨이퍼 레벨 패키지(WLP)'기술을 업계 최초로 개발했다고 밝혔다. 이 패키지 기술은 웨이퍼에서 잘라낸 칩 하나하나를 패키지하는 기존 방식과는 달리 칩이 분리되지 않은 웨이퍼 상에서 조립까지 끝마치는 혁신적인 반도체 패키지 기술이다.
하나의 반도체가 만들어지기까지는 회로설계, 웨이퍼가공, 조립(배선연결·패키지), 검사 등 4단계 과정을 거치게 된다. 이 가운데, 조립 공정은 가공이 끝난 웨이퍼에서 칩을 잘라낸 후 작은 회로기판(PCB)부착 및 배선연결(Wire Bonding) 과정을 거쳐 플라스틱 패키지를 씌우는 방식이었다.
'웨이퍼 레벨 패키지'방식은 패키지 재료로 사용되던 플라스틱 대신 웨이퍼에 구현된 각각의 칩 위에 감광성 절연물질을 입히고 배선연결 후 다시 절연물질을 덧 씌우는 간단한 절차로 패키지공정이 끝난다.
이 패키지 기술을 적용하면 배선연결(Wire Bonding)·플라스틱 패키지(Molding) 등 별도의 반도체 조립 과정이 단축됨은 물론, 기존의 반도체 조립에 쓰이던 플라스틱·회로기판(PCB)·배선연결용 와이어(Wire) 등이 불필요해 대폭적인 원가절감을 실현할 수 있게 된다.
특히, 칩과 동일한 크기로 패키지가 가능해 반도체의 소형화를 위해 적용돼 왔던 기존 CSP 방식의 패키지 보다도 20% 이상 패키지 크기를 줄일 수 있다. 이로써, 동일 면적의 메모리 모듈에 보다 많은 칩의 탑재가 가능해 짐으로써, 대용량 메모리 모듈제작이 한층 손쉬워 진다. ¶ 10:04 오전 0개의 덧글
신개념 반도체 조립기술 개발
[2004년 7월 뉴스파노라마]
지금까지 사용되던 반도체 패키지(조립) 방식과는 차원이 다른 신개념의 반도체 패키지 기술을 선보였다. 삼성전자는 반도체 칩을 분리하지 않은 Wafer 상태에서 칩에 패키지를 씌우는'웨이퍼 레벨 패키지(WLP)'기술을 업계 최초로 개발했다고 밝혔다. 이 패키지 기술은 웨이퍼에서 잘라낸 칩 하나하나를 패키지하는 기존 방식과는 달리 칩이 분리되지 않은 웨이퍼 상에서 조립까지 끝마치는 혁신적인 반도체 패키지 기술이다.
하나의 반도체가 만들어지기까지는 회로설계, 웨이퍼가공, 조립(배선연결·패키지), 검사 등 4단계 과정을 거치게 된다. 이 가운데, 조립 공정은 가공이 끝난 웨이퍼에서 칩을 잘라낸 후 작은 회로기판(PCB)부착 및 배선연결(Wire Bonding) 과정을 거쳐 플라스틱 패키지를 씌우는 방식이었다.
'웨이퍼 레벨 패키지'방식은 패키지 재료로 사용되던 플라스틱 대신 웨이퍼에 구현된 각각의 칩 위에 감광성 절연물질을 입히고 배선연결 후 다시 절연물질을 덧 씌우는 간단한 절차로 패키지공정이 끝난다.
이 패키지 기술을 적용하면 배선연결(Wire Bonding)·플라스틱 패키지(Molding) 등 별도의 반도체 조립 과정이 단축됨은 물론, 기존의 반도체 조립에 쓰이던 플라스틱·회로기판(PCB)·배선연결용 와이어(Wire) 등이 불필요해 대폭적인 원가절감을 실현할 수 있게 된다.
특히, 칩과 동일한 크기로 패키지가 가능해 반도체의 소형화를 위해 적용돼 왔던 기존 CSP 방식의 패키지 보다도 20% 이상 패키지 크기를 줄일 수 있다. 이로써, 동일 면적의 메모리 모듈에 보다 많은 칩의 탑재가 가능해 짐으로써, 대용량 메모리 모듈제작이 한층 손쉬워 진다. ¶ 10:04 오전 0개의 덧글
수요일, 2월 21, 2007
도요타 오디오
라디오는 변환기 사용해서 SBS빼고 다나오는거 같은데 워낙 라디오는 안 듣고 살아서리....
라디오는 변환기 사용해서 SBS빼고 다나오는거 같은데 워낙 라디오는 안 듣고 살아서리....
슬라이딩으로 내려가서 열리는 방식이네요.. ^^; 테이프는 없어서 사용못해봤네요...
¶ 7:06 오후 0개의 덧글
